The present invention relates to a memory device and a method for fabricating the same, and more particularly, to a non-volatile memory device and a method for fabricating the same.
Presently, among various non-volatile memory devices, NAND flash memory devices are widely used. In the memory devices, a plurality of memory cells that are coupled to each other in series configure to form a unit string, NAND flash memory devices are applied for high integration and can replace memory sticks, universal serial bus drivers (USBs), and hard disks.
Generally, in a NAND flash memory device, a plurality of memory cells for data storage (e.g., 16, 32, or 64 memory cells), a drain selection transistor that couples a drain of the first memory cell to a bit line, a source selection transistor that couples a source of the last memory cell to a common source line are coupled to each other in series to form one unit string.
FIG. 1 illustrates a circuit diagram of a memory cell array of a conventional NAND flash memory device. In this example, a string structure including 32 memory cells is illustrated.
The conventional NAND flash memory device includes a plurality of memory blocks, and a plurality of strings ST are placed in each of the memory blocks. Each of the strings ST includes a drain selection transistor, a source selection transistor, and a plurality of memory cells that are serially coupled together between the drain selection transistor and the source selection transistor. A source of the source selection transistor in each of the strings ST is coupled to a common source line. A gate of the drain selection transistor in each of the strings ST is coupled to a drain selection line DSL, and a gate of the source selection transistor in each of the strings ST is coupled to a source selection line SSL. Control gates of the memory cells are coupled to respective word lines WL0 to WL31. Reference denotations BL0 to BLn represents a plurality of bit lines prepared in n numbers, where n is a natural number.
As illustrated, since the memory cells in the NAND flash memory device are serially coupled together to form the unit string, the NAND flash memory device is prone to interference between neighboring peripheral memory cells. Thus, the state of the memory cells that configure the unit string (i.e., the threshold voltage) needs to be maintained consistent for reliable operation of the device and to further improve yields.
An interference effect refers to an incidence in which a threshold voltage of a selected memory cell changes due to an operation of a peripheral memory cell adjacent to the selected memory cell, particularly, a programming operation in relation to data storage. When a programming operation is performed for a second memory cell adjacent to a first memory cell selected to read data, capacitance between the first memory cell and the second memory cell changes due to electrons injected into a floating gate of the second memory cell. Further, when the first memory cell is read, the change in capacitance causes occasional reading of a voltage higher than the threshold voltage of the first memory cell. Although an amount of charges injected into the floating gate of the selected memory cell does not change, the threshold voltage of the selected memory cell is distorted due to the state change of the neighboring memory cell.
A threshold voltage of a memory cell for each word line within a string (a cell threshold voltage), after the programming operation, changes at least because of the interference effect. In particular, the word line WL0 illustrated in FIG. 1 is fabricated to have a larger line width in a horizontal direction and a wider space than the other word lines WL1 to WL31 for improving program disturbance with the neighboring source selection transistor. Depending on the need, even in the case where an etching is performed using an etch mask having the width as same as the word lines WL0 to WL31, the word line WL0 is formed to have a larger width than the other word lines WL1 to WL30 according to the pattern density of the word lines WL0 to WL31. Thus, under the same condition, the word line WL0 usually has a voltage higher than a program threshold voltage of the other word lines WL1 to WL31.
FIG. 2 illustrates a graph of cell threshold voltage distribution for each word line. The threshold voltage of each of the memory cells within the same string is measured after the performance of a programming operation for the same string under the same condition. In this graph, the cell threshold voltage Cell VT is expressed in a horizontal X axis, and the number of the memory cells is expressed in a vertical Y axis.
Even if the program operation is performed for the same string under the same condition, the threshold voltage of the memory cell coupled to a word line WL0, adjacent to a source selection transistor, is relatively higher than the threshold voltages of the memory cells respectively coupled to the word lines WL1 to WL30. The threshold voltage of the memory cell coupled to the word line WL31 is low.
The above-described result is caused due to the interference effect. Thus, it is necessary to secure uniformity in the cell threshold voltage for each word line within the same string in order to improve reliability of devices. Further, it is to be understood that the afore-mentioned limitation is not only for the conventional NAND flash memory device, but also for many types of memory devices configured with the string structure.